Frequency multiplier using 50% duty cycle corrector
نویسندگان
چکیده
منابع مشابه
Simple odd number frequency divider with 50% duty cycle
A simple odd number frequency divider with 50% duty cycle is presented. The odd number frequency divider consists of a general odd number counter and the proposed duty cycle trimming circuit. The duty cycle trimming circuit can output 50% duty cycle with only additional six transistors. A prototype divide-by-5 circuit with 50% duty cycle was implemented for a 500-Mb/s ∼ 5.6-Gb/s 1:10 CDR/DEMUX ...
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This concise presents a Modified Successive Approximation Register (MSAR)-based duty cycle corrector (DCC), which achieves low jitter, fast lock time with an accurate 50% duty cycle correction. This Modified SAR adopts a binary search method to condense lock time while maintaining tight synchronization between effort and production clocks. The projected DCC consists of a duty-cycle detector, a ...
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This paper presents considerations on the switching frequency and duty cycle & operating equations of softswitching BUCK chopper. These considerations are discussed and applied to selected soft-switching families such as ZVS-QRC, ZCS-QRC, ZVS-QSW-CV, ZCS-QSWCC, ZVT-PWM and ZCT-PWM [1]. The limitations on switching frequency and duty cycle are derived in terms of: chopper input voltage (Vg), cho...
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Novel frequency doubler circuits and dividers for clock signal generation are presented. In combination with two edge detectors and two duty cycle control buffers a low cost frequency doubler circuit is achieved as compared to Phase-Locked Loop (PLL) design. An input clock signal with an unpredictable duty cycle is inputted to a rising (or falling) edge detector. The edge detector converts the ...
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ژورنال
عنوان ژورنال: IEICE Electronics Express
سال: 2008
ISSN: 1349-2543
DOI: 10.1587/elex.5.990